Thin film transistor and manufacturing method thereof, array substrate, and display device

ABSTRACT

The technical disclosure relates to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a base substrate, a gate electrode, an active layer, source/drain electrodes, a pixel electrode and one or more insulating layers, wherein at least one of the insulating layers comprises a bottom insulating sub-layer and a top insulating sub-layer, the top insulating sub-layer having a hydrogen content higher than that of the bottom insulating sub-layer.

TECHNICAL FIELD

Embodiments of the present technical disclosure relate to a thin filmtransistor (TFT) technology in the field of liquid crystal display.

BACKGROUND

FIG. 1 shows a structure of a traditional oxide semiconductor thin filmtransistor (oxide thin film transistor). As shown in FIG. 1, thetraditional oxide thin film transistor comprises, sequentially frombottom up, a base substrate 10, a gate electrode 11, a gate insulatinglayer 12, an active layer 13, an etch stop layer 14, source/drainelectrodes 15, a protective layer 16 and a pixel electrode 17.

FIGS. 2 (a) to 2 (g) show a traditional method of manufacturing theoxide thin film transistor. As shown in FIG. 2 (a), the traditionalmanufacturing method comprises firstly forming the gate electrode 11 onthe base substrate 10; as shown in FIG. 2 (b), forming the gateinsulating layer 12, which covers the substrate 10 and the gateelectrode 11; as shown in FIG. 2 (c), forming the active layer 13 on thegate insulating layer 12 corresponding to the gate electrode 11, theactive layer 13 being made of an oxide semiconductor material (e.g.,indium gallium zinc oxide (IGZO)); as shown in FIG. 2 (d), forming theetch stop layer 14 on the active layer 13; as shown in FIG. 2 (e),forming the source/drain electrodes 15 on the etch stop layer 14; asshown in FIG. 2 (f), then forming the protective layer 16 to cover thesource/drain electrodes 15, the etch stop layer 14 and the gateinsulating layer 12; and as shown in FIG. 2 (g), finally forming thepixel electrode 17 on the source/drain electrode 15 and the protectivelayer 16.

Compared with the process of manufacturing the amorphous silicon (a-Si)thin film transistor, the process of manufacturing the oxide thin filmtransistor has an additional process for forming the etch stop layer(i.e., the step shown in FIG. 2 (d)). The characteristics of the oxidethin film have greatly affected by the interfacial characteristics,especially the thin film deposition process of the etch stop layer,which requires for example the silicon oxide thin film manufactured inthe process for forming the etch stop layer to maintain a low content ofhydrogen, generally lower than 6%; in contrast, in the amorphous siliconthin film transistor, the silicon nitride thin film has a hydrogencontent of about 20%. On one hand, the purpose of the process forforming the etch stop layer is to prevent the etchant from corroding theactive layer when performing etching process on the source/drainelectrodes; on the other hand, the etch stop layer is usually formed bythe silicon oxide materials, and in order to maintain a low hydrogencontent of the silicon oxide thin film, the plasma enhanced chemicalvapor deposition (PECVD) method is usually adopted to deposit thesilicon oxide thin film. When the PECVD method is used, the hydrogenions generated by silane decomposition are prone to react with In, Zn, Oin the metal oxides (e.g., IGZO) in the active layer, affecting thecharacteristics of the IGZO thin film. Accordingly, the currentlyadopted solution is to lower the deposition temperature to about 200□,but it may increase the hydrogen content in the deposited silicon oxidethin film in the condition that the reaction gas has a constant flowrate, and thus the stability of the thin film is deteriorated and thedeposition rate of the thin film is reduced.

SUMMARY

One aspect of the present technical disclosure provides a thin filmtransistor, which comprises a base substrate, a gate electrode, anactive layer, source/drain electrodes, a pixel electrode and one or moreinsulating layers; at least one of the insulating layers comprises abottom insulating sub-layer and a top insulating sub-layer, and the topinsulating sub-layer has a hydrogen content higher than that of thebottom insulating sub-layer.

For example, the thin film transistor is an oxide thin film transistor,which comprises a plurality of insulating layers; the insulating layerscomprises a gate insulating layer, an etch stop layer and a protectivelayer, the etch stop layer comprises a bottom etch stop layer as thebottom insulating sub-layer and a top etch stop layer as the topinsulating sub-layer, and the top etch stop layer has a hydrogen contenthigher than that of the bottom etch stop layer.

For example, in the oxide thin film transistor, the hydrogen content ofthe top etch stop layer is 5%˜10%, and the hydrogen content of thebottom etch stop layer is 1%˜5%.

For example, in the oxide thin film transistor, the gate electrode isdisposed on the base substrate; the gate insulating layer covers thesubstrate and the gate electrode; the active layer is disposed on thegate insulating layer corresponding to the gate electrode; the bottometch stop layer is disposed on the active layer; the top etch stop layeris disposed on the bottom etch stop layer: the source/drain electrodesare disposed on the top etch stop layer; the protective layer covers thegate insulating layer, the source/drain electrodes and the top etch stoplayer; and the pixel electrode is disposed on the source/drainelectrodes and the protective layer.

For example, in the oxide thin film transistor, the bottom etch stoplayer has a thickness of 200-1000 Å, and the top etch stop layer has athickness of 1000-1500 Å.

For example, in the thin film transistor, the active layer is made ofindium gallium zinc oxide semiconductor or indium zinc oxidesemiconductor.

For example, in the thin film transistor, the active layer is depositedby magnetron sputtering.

Another aspect of the present technical disclosure provides an arraysubstrate, which comprises the aforementioned thin film transistor.

Further another aspect of the present technical disclosure provides adisplay device, which comprises the aforementioned array substrate.

Still further aspect of the present technical disclosure provides amethod of manufacturing a thin film transistor, comprising: forming agate electrode, an active layer, source/drain electrodes, one or moreinsulating layers and a pixel electrode on a base substrate, andsequentially forming a bottom insulating sub-layer and a top insulatingsub-layer when forming at least one of the insulating layers such thatthe top insulating sub-layer has a hydrogen content higher than that ofthe bottom insulating sub-layer.

For example, the thin film transistor is an oxide thin film transistor,the at least one of the insulating layers comprises an etch stop layer,and the manufacturing method comprises: sequentially forming the gateelectrode, a gate insulating layer, the active layer, an etch stoplayer, the source/drain electrodes, a protective layer, and the pixelelectrode on a base substrate, and sequentially forming a bottom etchstop layer as the bottom insulating sub-layer and a top etch stop layeras the top insulating sub-layer when forming the etch stop layer suchthat the top etch stop layer has a hydrogen content higher than that ofthe bottom etch stop layer.

For example, the manufacturing method comprises: forming the gateelectrode on the base substrate; forming the gate insulating layercovering the base substrate and the gate electrode; forming the activelayer on the gate insulating layer corresponding to the gate electrode;forming the bottom etch stop layer on the active layer; forming the topetch stop layer on the bottom etch stop layer; forming the source/drainelectrodes on the top etch stop layer; forming the protective layercovering the gate insulating layer, the source/drain electrodes and thetop etch stop layer; and forming the pixel electrode on the source/drainelectrodes and the protective layer.

For example, in the method, the bottom etch stop layer is deposited at200-300° C. with a silane gas flow rate of 300-800 sccm; the top etchstop layer is deposited at 240-340° C. with a silane gas flow rate of600-1200 sccm.

For example, in the method, the bottom etch stop layer is deposited witha thickness of 200-1000 Å, and the top etch stop layer is deposited witha thickness of 1000-1500 Å.

For example, in the method, the active layer is made of indium galliumzinc oxide semiconductor or indium zinc oxide semiconductor.

For example, in the method, the active layer is deposited by magnetronsputtering.

Further scope of applicability of the present technical disclosure willbecome apparent from the detailed description given hereinafter.However, it should be understood that the detailed description andspecific examples, while indicating preferred embodiments of thetechnical disclosure, are given by way of illustration only, sincevarious changes and modifications within the spirit and scope of thetechnical disclosure will become apparent to those skilled in the artfrom the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The present technical disclosure will become more fully understood fromthe detailed description given hereinafter and the accompanying drawingswhich are given by way of illustration only, and thus are not limitativeof the present technical disclosure and wherein:

FIG. 1 is a structural schematic view of a traditional oxide thin filmtransistor;

FIGS. 2 (a)-2 (g) are schematic flow charts of manufacturing thetraditional oxide thin film transistor;

FIG. 3 is a structural schematic view of an oxide thin film transistoraccording to an embodiment of the present technical disclosure; and

FIG. 4 is a schematic flow chart of manufacturing the oxide thin filmtransistor according to an embodiment of the present technicaldisclosure.

Reference Signs:

10, 20-substrate; 11, 21-gate electrode; 12, 22-gate insulating layer;13, 23-active layer; 14-etch stop layer; 24 a bottom etch stop layer asthe bottom insulating sub-layer; 24 b-top etch stop layer; 15,25-source/drain electrodes; 16, 26-protective layer; 17, 27-pixelelectrode.

DETAILED DESCRIPTION

According to the traditional TFT manufacturing process in the backgroundportion of the present disclosure, it becomes a problem to be solved inthe related technical field how to improve the structure andmanufacturing process of the oxide thin film transistor, e.g., to lowerthe hydrogen content in the silicon oxide thin film for the etch stoplayer, to maintain excellent characteristics of the oxide thin filmtransistor, and to improve the deposition rate of the thin film of theetch stop layer.

In one embodiment of the present technical disclosure, at lease oneinsulating layer of the thin film transistor is manufactured by adouble-layer structure process, i.e., to manufacture the bottominsulating sub-layer and the top insulating sub-layer respectively, sothat different process conditions can be used to manufacture the bottominsulating sub-layer and the top insulating sub-layer according to theproperties of the insulating layer thin film.

The thin film transistor and the manufacturing method thereof accordingto the embodiments of the present technical disclosure will be hereindescribed in details with reference to the drawings by taking the etchstop layer in the oxide thin film layer as an example.

Unless otherwise defined, the technical or scientific terms used hereinshall have the general meanings understandable for those ordinarilyskilled in the field of the present technical disclosure. The words suchas “a”, “an”, “the” or the like shall not represent limitation ofnumbers, but mean existence of at least one. The words “comprise”,“include” or the like intend to mean the elements or objects before suchwords cover or are equivalent to the elements or objects listed aftersuch words, but other elements or objects are not exclusive. The words“joint”, “connect” or the like are not limited to physical or chemicalconnection, but also comprise electrical connection, no matter directlyor indirectly. The words “upper”, “lower”, “left”, “right” and etc.shall be used only to represent relative positions, wherein, when theabsolute position of the described object is changed, the relativepositions may be changed accordingly.

FIG. 3 shows the structure of the oxide thin film transistor in oneembodiment of the present technical disclosure. As shown in FIG. 3, theoxide thin film transistor of the present embodiment comprises: a basesubstrate 20, a gate electrode 21, a gate insulating layer 22, an activelayer 23, an etch stop layer 24, source/drain electrodes 25, aprotective layer 26 and a pixel electrode 27. With respect to the basesubstrate 20, the etch stop layer 24 comprises a bottom etch stop layeras the bottom insulating sub-layer 24 a and a top etch stop layer as thetop insulating sub-layer 24 b, and the top etch stop layer 24 b has ahydrogen content higher than that of the bottom etch stop layer 24 a.

The etch stop layer will be doped with hydrogen ions during themanufacturing process. In order to maintain the hydrogen content at alow level, the flow rate of the silane gas shall be reduced, whichhowever will affect the speed of depositing the thin film; if a higherspeed of depositing the thin film is maintained, the hydrogen content inthe thin film will be increased. So, if the etch stop layer in the twolayer structure is manufactured such that the upper layer has a higherhydrogen content and the lower layer has a lower hydrogen content, theinfluence of the hydrogen ions in the etch stop layer on the oxidesemiconductor active layer can be lowered while the deposition speed isnot affected.

For example, the hydrogen content in the top etch stop layer 24 b may be5%˜10%, and the hydrogen content in the bottom etch stop layer 24 a maybe 1%˜5%.

Under the condition of the exemplary hydrogen content, the oxide thinfilm transistor to be manufactured will have a better performance whilethe deposition speed may be optimized.

As shown in FIG. 3, the gate electrode 21 is formed on the basesubstrate 20; the gate insulating layer 22 covers the base substrate 20and the gate electrode 21; the active layer 23 is formed on the gateinsulating layer 22 corresponding to the gate electrode 21; the bottometch stop layer 24 a is formed on the active layer 23; the top etch stoplayer 24 b is formed on the bottom etch stop layer 24 a; thesource/drain electrodes 25 are formed on the top etch stop layer 24 b;the protective layer 26 covers the gate insulating layer 22, thesource/drain electrodes 2S and the top etch stop layer 24 b; and thepixel electrode 27 is formed on the source/drain electrodes 25 and theprotective layer 26.

In order to improve the properties of the oxide thin film transistor,the above embodiment adopts a double-layered etch stop layer, i.e., thebottom etch stop layer 24 a and the top etch stop layer 24 b arerespectively disposed. In forming of the bottom etch stop layer 24 a, alower deposition temperature and a lower silane gas flow rate areadopted so that the content of hydrogen ions generated by silanedecomposition in the reaction gas is reduced, thereby avoiding theproperties of the oxide thin film transistor from beingdisadvantageously affected by the reaction between hydrogen ions and In,Zn, O and etc. in metal oxides such as IGZO in the active layer. Informing of the top etch stop layer 24 b, a higher deposition temperatureand a higher silane gas flow rate are adopted, the silane in thereaction gas is sufficiently decomposed because of the higher depositiontemperature. In addition, although the deposition temperature and thesilane gas flow rate are higher such that the hydrogen ion concentrationgenerated by the silane decomposition is higher, the bottom etch stoplayer 24 a prevents the contact between the metal oxides such as IGZO inthe active layer and the hydrogen ions so as to avoid the hydrogen ionsfrom reacting with the In, Zn, O and etc. in the metal oxides such asIGZO. In this case, the properties of the oxide thin film transistorwill not be disadvantageously affected while the hydrogen content in thetop etch stop layer 24 b is higher than the hydrogen content in thelower etch stop layer 24 a. Therefore, the hydrogen content in thesilicon oxide thin film is effectively lowered, the oxide thin filmtransistor maintains good properties and improved stability, and thedeposition rate of the etch stop layer thin film is improved as well.

What is needed to be explained is that both the reaction temperature andthe silane gas flow rate in the reaction gas will affect the hydrogencontent generated by silane decomposition in the reaction gas when theetch stop layer is deposited. When the reaction temperature is constant,the lower the silane gas flow rate is, the more sufficiently the silaneis decomposed, the lower the hydrogen content in the formed siliconoxide thin film is, but the deposition rate will be lowered accordingly.On the other hand, when the reaction temperature is constant, although ahigher silane gas flow rate can help to improve the deposition rate, itis easy to cause insufficient decomposition of the silane gas and isunfavorable to lower the hydrogen content in the silicon oxide thinfilm. Therefore, the silane gas flow rate shall be appropriatelydetermined according to the temperature and the practical requirementsof production. Moreover, when the silane gas flow rate is constant, thehigher the temperature is, the more sufficiently the silane isdecomposed, the more hydrogen ions are generated, and the quick thedeposition rate is. But it is easy to cause reaction between thehydrogen ions and the In, Zn, O and etc. in the metal oxides such asIGZO, thus disadvantageously affecting the properties of the oxide thinfilm transistor. Therefore, the deposition rate and the properties ofthe thin film shall be taken into comprehensive consideration, and thereaction temperature and the silane gas flow rate in the reaction gasshall be appropriately set.

On the basis of taking the deposition rate and the properties of thethin film into comprehensive consideration, one example in theembodiment of the present technical disclosure sets the depositiontemperature of the bottom etch stop layer to be 200-300° C., preferably250° C., the silane gas flow rate to be 300-800 sccm (standard cubiccentimeter per minute), preferably 600 sccm, and the deposition power tobe 6000 W, such that the hydrogen content generated by silanedecomposition in the reaction gas is lowered and the hydrogen ions areprevented from reacting with the In, Zn, O and etc. in the metal oxidessuch as IGZO in the active layer. For the top etch stop layer, thedeposition temperature is set to be 240-340° C., preferably 290° C.,such that the silane in the reaction gas may be decomposed moresufficiently and the hydrogen content in the oxide thin film may belowered. The silane gas flow rate may be determined according to thepractical requirements of product, and higher silane gas flow rate mayhelp to improve the deposition rate of the thin film. In order toimprove the deposition rate of the thin film, in one example of theembodiments of the present technical disclosure, the silane gas flowrate is 600-1200 sccm, preferably 900 sccm, and the deposition rate is3500 W.

By the above setting of the process conditions, the embodiments of thepresent technical disclosure can reduce the hydrogen content in thesilicon oxide thin film in the bottom etch stop layer to about 3%, andreduce the hydrogen content in the silicon oxide thin film in the topetch stop layer to about 5% (the traditionally manufactured siliconoxide thin film has a hydrogen content of about 6%).

Furthermore, the setting of the thickness of the bottom etch stop layeror the top etch stop layer also affects the overall deposition rate andthe properties of the etch stop layer thin film. The embodiments of thepresent technical disclosure take the deposition rate and the propertiesof the thin film into comprehensive consideration, for example, thebottom etch stop layer has a thickness of 200-1000 Å, preferably 500 Å,and the top etch stop layer has a thickness of 1000-1500 Å, preferably1500 Å.

In addition, in order to improve adhesion between the silicon oxide thinfilm and the photoresist, for example, an adhesive layer (not shown) maybe further added between the top etch stop layer and photoresist appliedfor patterning; and the adhesive layer usually is a layer of siliconnitride thin film of several hundred angstroms.

The thin film in each layer in the oxide thin film transistor of thepresent technical disclosure may be manufactured by the traditionalmethods and materials for thin films. For example, the gate electrodemay be made of a single-layer film of AlNd, Al, Cu, Mo, MoW or Cr, or acomposite film of any combination of AlNd, Al, Cu, Mo, MoW or Cr; thegate insulating layer may by made of a thin film of silicon nitride(SiNx) or silicon oxide (SiO₂); the active layer may be made of indiumzinc oxide (IZO) or doped IZO (e.g., indium gallium zinc oxide (IGZO))semiconductor by magnetron sputtering.

In order to realize the aforementioned oxide thin film transistor,another embodiment of the present technical disclosure provides a methodof manufacturing an oxide thin film transistor. As shown in FIG. 4, themanufacturing method of the present technical disclosure comprises thefollowing steps:

Step 2 a: forming a gate electrode 21 on a substrate;

Step 2 b: forming a gate insulating layer 22 covering the substrate 20and the gate electrode 21;

Step 2 c: forming an active layer 23 on the gate insulating layer 22corresponding to the gate electrode 21;

Step 2 d: forming a bottom etch stop layer 24 a on the active layer 23;

Step 2 e: forming a top etch stop layer 24 b on the bottom etch stoplayer 24 a;

Step 2 f: forming source/drain electrodes 25 on the top etch stop layer24 b;

Step 2 g: forming a protective layer 26 covering the gate insulatinglayer 22, the source/drain electrodes 25 and the top etch stop layer 24b; and

Step 2 h: forming a pixel electrode 27 on the source/drain electrodes 25and the protective layer 26.

The above steps are shown as steps 2 a-2 g in FIG. 4 correspondingly.

The thin film of the aforementioned each layer may be manufactured bythe traditional methods and materials for thin films. For example, instep 2 a, the gate electrode may be made of a single-layer film of AlNd,Al, Cu, Mo, MoW or Cr, or a composite film of any combination of AlNd,Al, Cu, Mo, MoW or Cr; for example, in step 2 b, the gate insulatinglayer may by made of a thin film of silicon nitride (SiNx) or siliconoxide (SiO₂); for example, in step 2 c, the active layer may be made ofindium gallium zinc oxide (IGZO) or indium zinc oxide (IZO)semiconductor by magnetron sputtering.

Furthermore, the embodiments of the present technical disclosure takethe influence of the deposition temperature, the saline gas flow rateand the thin film deposition thickness on the properties and thedeposition rate of oxide thin film transistor into comprehensiveconsideration. In one example, for example, in step 2 d, the depositiontemperature of the bottom etch stop layer is 200-300° C., preferably250° C., for example, the silane gas flow rate is 300-800 sccm,preferably 600 sccm, the deposition power is 6000 W, and the depositionthickness is 200-1000 Å, preferably 500 Å; for example, in step 2 e, thedeposition temperature of the top etch stop layer is 240-340° C.,preferably 290° C., for example, the silane gas flow rate is 600-1200sccm, preferably 900 sccm, the deposition power is 3500 W, and thedeposition thickness is 1000-1500 Å, preferably 1500 Å.

In addition, in order to improve adhesion between the silicon oxide thinfilm and the photoresist applied for patterning, for example, anadhesive layer (not shown) may be added between the top etch stop layerand the photoresist; and the adhesive layer usually is a layer ofsilicon nitride thin film of several hundred angstroms.

Compared with the traditional process shown in FIGS. 2 (a)-2 (g), thethin film transistor provided by the embodiments of the presenttechnical disclosure manufacture etch stop layer with a double-layeredstructure, which has the following advantages: (1) in the process ofmanufacturing the bottom etch stop layer, although a depositiontemperature lower than that of the traditional process is used, thelower silane gas flow rate is adopted such that the silane decompositionis more sufficient; furthermore, the flow rate in the bottom etch stoplayer is lower than that in the top etch stop layer such that theconcentration of the hydrogen ions generated by the silane decompositionin the bottom layer is lower than that of the upper insulating layer,whereby the hydrogen content in the etch stop layer is further reduced;(2) when the top etch stop layer is deposited, the bottom etch stoplayer can prevent the generated hydrogen ions from reacting with themetal oxide in the active layer, such that the top etch stop layer canbe deposited at a high temperature and a high silane gas flow rate.Therefore, the reaction between the hydrogen ions generated by silanedecomposition and the metal oxide in the active layer is prevented, andthe deposition rate of the etch stop layer thin film is improved.

The above description takes the etch stop layer in the oxide thin filmtransistor for example to illustrate the thin film transistor and themanufacturing method thereof in the embodiments of the present technicaldisclosure. It shall be noted that the aforementioned process parameterscomprising temperature, gas flow rate, deposition power, thickness ofthe thin film and etc. are all exemplary process parameters, and theembodiments of the present technical disclosure are not limited thereto.Those skilled in the art are able to adjust the process parametersaccording to the practical needs.

In addition, the process of manufacturing the insulating layer with adouble-layered structure in the embodiments of the present technicaldisclosure shall not be limited to the etch stop layer made of e.g.,silicon oxide in the oxide thin film transistor, it is also applied tothe protective layer made of e.g., silicon oxide in the oxide thin filmtransistor, or the etch stop layer or the protective layer made of e.g.,silicon nitride in the oxide thin film transistor or amorphous siliconthin film transistor. The specific principles are similar to those ofthe etch stop layer in the oxide thin film transistor, so no moredetails are dealt with herein.

A further embodiment of the present technical disclosure provides anarray substrate, which comprises the aforementioned thin filmtransistor, the thin film transistor for example serving as a switchelement of a pixel unit. For example, the array substrate of theembodiment comprises a plurality of gate lines and a plurality of datalines which intersect each other to define pixel units arranged in amatrix, each pixel unit comprising a thin film transistor as a switchelement, and a pixel electrode for controlling orientation of liquidcrystal. For example, a gate electrode of the thin film transistor ineach pixel is electrically connected to or integrally formed with acorresponding gate line, a source electrode thereof is electricallyconnected to or integrally formed with a corresponding data line, and adrain electrode thereof is electrically connected to or integrallyformed with a corresponding pixel electrode.

A further embodiment of the present technical disclosure provides adisplay device, which comprises the aforementioned array substrate. Forexample, the display device may be a liquid crystal display, an organiclight emitting diode (OLED) display, and so on.

In the liquid crystal display, the array substrate and an opposedsubstrate are disposed opposite to each other so as to form a liquidcrystal cell, and a liquid crystal material is filled in the liquidcrystal cell. The opposed substrate is, for example, a color filtersubstrate. In some examples, the liquid crystal display device furthercomprises a backlight module used to provide light source for the arraysubstrate. In the OLED, the lamination of organic light emittingmaterials is formed on the array substrate, and the pixel electrode ineach pixel unit is used as anode or cathode for driving the organiclight emitting materials to emit light, so as to conduct a displayoperation.

The above embodiments of the present technical disclosure are preferableembodiments only and thus are not limitative of the protection scope ofthe present technical disclosure.

What is claimed is:
 1. A thin film transistor, comprising: a basesubstrate, a gate electrode, an active layer, source/drain electrodes, apixel electrode and one or more insulating layers, wherein at least oneof the insulating layers comprises a bottom insulating sub-layer and atop insulating sub-layer, the top insulating sub-layer having a hydrogencontent higher than that of the bottom insulating sub-layer.
 2. The thinfilm transistor according to claim 1, wherein the thin film transistoris an oxide thin film transistor, which comprises a plurality ofinsulating layers, the insulating layers comprising a gate insulatinglayer, an etch stop layer and a protective layer, the etch stop layercomprising a bottom etch stop layer as the bottom insulating sub-layerand a top etch stop layer as the top insulating sub-layer, the top etchstop layer having a hydrogen content higher than that of the bottom etchstop layer.
 3. The thin film transistor according to claim 2, whereinthe hydrogen content of the top etch stop layer is 5%˜10%, and thehydrogen content of the bottom etch stop layer is 1%˜5%.
 4. The thinfilm transistor according to claim 2, wherein, in the oxide thin filmtransistor, the gate electrode is disposed on the base substrate; thegate insulating layer covers the substrate and the gate electrode; theactive layer is disposed on the gate insulating layer corresponding tothe gate electrode; the bottom etch stop layer is disposed on the activelayer; the top etch stop layer is disposed on the bottom etch stoplayer; the source/drain electrodes are disposed on the top etch stoplayer; the protective layer covers the gate insulating layer, thesource/drain electrodes and the top etch stop layer; and the pixelelectrode is disposed on the source/drain electrodes and the protectivelayer.
 5. The thin film transistor according to claim 2, wherein thebottom etch stop layer has a thickness of 200-1000 Å, and the top etchstop layer has a thickness of 1000-1500 Å.
 6. The thin film transistoraccording to claim 2, wherein the active layer is made of indium galliumzinc oxide semiconductor or indium zinc oxide semiconductor.
 7. An arraysubstrate, comprising a thin film transistor according to claim
 1. 8. Adisplay device, comprising an array substrate according to claim 7.